System and Method of Compensating for the Effects of On-Chip Processing Variation on an Integrated Circuit

ABSTRACT

A system and method of compensating for effects of on-chip processing variation on an integrated circuit. The integrated circuit is divided into a set of regions. Then, a region control logic, included in each region, predicts a processing variation in each respective region of the integrated circuit. Finally, each region control logic automatically selects one of a set of available power settings to power each one of the respective regions, in response to the region control logic predicting the processing variation, wherein the processing variation of each of the set of regions is minimized.

The present application is a divisional of U.S. patent application Ser.No. 11/082,927 (Atty. Docket No. ROC920050011US1), filed on Mar. 17,2005, and entitled, “System and Method of Compensating for the Effectsof On-Chip Processing Variation on an Integrated Circuit,” which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates in general to integrated circuits. Moreparticularly, the present invention relates to providing power tointegrated circuits. Still more particularly, the present inventionrelates to a system and method of compensating for effects of on-chipprocessing variation on an integrated circuit.

2. Description of the Related Art

As integrated circuits increase in size and complexity, improvements inlithography have led to smaller device dimensions and interconnectpitches. The reduction of device dimensions and interconnect pitchescontribute to increased relative variation in processing across eachintegrated circuit. Several properties such as effective channel length,gate oxide thickness, threshold voltages, and other device parametersvary over a single integrated circuit. These device parameter variationsaffect device characteristics, which contribute to variations inoperating frequency and power dissipation across the integrated circuit.

FIG. 2 is a pictorial representation of on-chip processing variationacross a critical path on an integrated circuit 200 according to theprior art. Included in integrated circuit 200 are exemplary circuits 208a-208 e. Circuits 208 a-208 e, coupled by interconnect 210, form a pathacross integrated circuit 200. Also, as illustrated in FIG. 2, regions202, 204, and 206 define regions on integrated circuit 200 where theprocessing in those regions are characterized as “slow”, “nominal”, and“fast”, respectively. Those with skill in this art will appreciate thatregions with processing characterized as “slow” typically limit thefrequency in which a signal may propagate through the region. Anintegrated circuit designer can remedy this problem by increasing thesupply voltage. Consequently, regions with processing characterized as“fast” typically operate at a higher frequency at the same voltagesetting as a “slow” region. The “fast” regions of an integrated circuitcontribute to DC leakage currents. As well-known to those with skill inthis art, integrated circuit 200 is typically coupled to a single powersupply (not illustrated in FIG. 2). The region with processingcharacterized as “slow” limits the cycle time and the maximum operatingfrequency of integrated circuit 200. Likewise, the region withprocessing characterized as “fast” contribute to power consumption ordissipation through DC leakage currents. If a designer utilizesintegrated circuit 200 in a power-sensitive application, raising thesupply voltage often requires the designer to lower the operatingfrequency to reduce the power dissipation effects of “fast” regions.Therefore, there is a need for a system and method of minimizingdifferences in frequency and power dissipation across various regions ofan integrated circuit.

SUMMARY OF THE INVENTION

A system and method of compensating for effects of on-chip processingvariation on an integrated circuit is disclosed. The integrated circuitis divided into a set of regions. Then, region control logic, includedin each region, predicts a processing variation in each respectiveregion of the integrated circuit. Finally, each region control logicautomatically selects one of a set of available power settings to powereach one of the respective regions, in response to the region controllogic predicting the processing variation, wherein the processingvariations of each of the set of regions are minimized.

The above as well as additional objects, features, and advantages of thepresent invention will become apparent in the following detailed writtendescription.

BRIEF DESCRIPTION OF THE FIGURES

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, further objects and advantages thereof, willbest be understood by reference to the following detailed description ofan illustrative embodiment when read in conjunction with theaccompanying drawings, wherein:

FIG. 1 is a block diagram illustrating an exemplary data processingsystem in which a preferred embodiment of the present invention may beimplemented;

FIG. 2 is a pictorial representation of on-chip processing variationacross a critical path on an integrated circuit according to the priorart.

FIG. 3 is a block diagram illustrating a method of dividing anintegrated circuit into various regions according to a preferredembodiment of the present invention;

FIG. 4 is a block diagram depicting an exemplary integrated circuit inwhich a preferred embodiment of the present invention may beimplemented;

FIG. 5 is a circuit diagram illustrating a region control logic unit inwhich a preferred embodiment of the present invention may beimplemented; and

FIG. 6 is a high-level logical flowchart depicting a method ofcompensating for effects of on-chip property variations according to apreferred embodiment of the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

The present invention provides a method and an integrated circuitdesign/configuration by which effects of on-chip property variations canbe minimized. On-chip property variations affect both the frequency andpower dissipation characteristics of various regions of an integratedcircuit. The present invention enables dynamic analysis of theintegrated circuit and varies the voltage setting of a power supplyutilized by specific regions of the integrated circuit, depending on theresults of an analysis of the signal propagation of the region. Thepresent invention also enables power distribution within each of thevarious regions which is physically and electrically separate from otherregions in the integrated circuit.

With reference now to the figures and in particular, with reference toFIG. 1, there is depicted an exemplary data processing system 100 inwhich a preferred embodiment of the present invention may beimplemented. As illustrated, a collection of processors 102 a to 102 nare coupled to system memory 114 via an interconnect 116. Processors 102a to 102 n are exemplary integrated circuits in which a preferredembodiment of the present invention may be implemented. System memory114 is preferably implanted as a dynamic random access memory (DRAM)module, but those skilled in this art will appreciate that system memory114 may alternatively be implemented as a hard disk, optical drive, orflash memory. Data processing system 100 preferably supports a varietyof input/output (I/O) components, such as one conforming to IndustryStandard Architecture (ISA), Advanced Graphics Port (AGP), andPeripheral Component Interconnect (PCI) standards, via a system I/Ocontroller 104. Also, mezzanine bus 118 couples PCI host bridge 108 tosystem I/O controller 104. Coupled to PCI host bridge 108 are a varietyof PCI adapters 112, which may be implemented as audio cards, networkinterface cards (NIC), modems, or any other PCI components.

Those skilled in this art will appreciate that data processing system100 can include many additional components not specifically illustratedin FIG. 1. Because such additional components are not necessary for anunderstanding of the present invention, they are not illustrated in FIG.1 or discussed further herein. It should also be understood, however,that the system and method for mitigating the effects of on-chipprocessing variation in frequency and power dissipation provided by thepresent invention are applicable to data processing systems of anysystem architecture and are in no way limited to the generalizedmulti-processing (MP) architecture or symmetric multi-processor (SMP)system structure illustrated in FIG. 1.

FIG. 3 is a pictorial representation of the distribution of circuitsamong a set of defined regions on an integrated circuit according to apreferred embodiment of the present invention. Integrated circuit 300includes circuits 308 a-308 e, each coupled to another circuit viainterconnect 310. Integrated circuit 300 is also divided into regions350-380. According to a preferred embodiment of the present invention,each region 350-380 includes a respective region control logic 500. Eachregion control logic 500 measures the signal propagation frequency inits respective region and sends the measured signal propagationfrequency to central control logic 410 via data bus 406, both discussedherein in more detail in conjunction with FIG. 4. Those with skill inthis art will appreciate that the signal propagation frequency of eachregion may be measured with a qualitative label, such as “fast”,“nominal”, or “slow”. Other ways of characterizing the signalpropagation frequency of each region may involve assigning a value toeach region where “0” is nominal and any integer (e.g., 1, −1, 2, 4, −6)determines which power setting the specific region should select inoptimizing the design.

FIG. 4 illustrates a second representation of an exemplary integratedcircuit in which a preferred embodiment of the present invention may beimplemented. FIG. 4 depicts VDD0 lines 402 and VDD1 lines 404, which aretwo power supplies available for powering each region 350-380. Asillustrated, integrated circuit 300 also includes data bus 406 andaddress bus 408, which enable communication between central controllogic 410 and each region control logic 500. Central control logic 410collects the signal propagation frequency measurements from each regioncontrol logic 500 and selects from a set of available voltage settingsfor assignment to each region 350-380.

As discussed later in more detail in conjunction with FIG. 5, theinteraction between central control logic 410 and each region controllogic 500 is dynamic. During operation, central control logic 410 andeach region control logic 500 constantly measure the signal propagationfrequency of each region and adjust the assignment of voltage settingsas needed.

With reference now to FIG. 5, there is depicted a circuit diagram ofregion control logic 500 according to a preferred embodiment of thepresent invention. As described above, region control logic 500 measuresthe signal propagation frequency of the respective region, as indicatedby circuits 504, by comparing the measured signal propagation frequencywith a default signal propagation frequency sent by central controllogic 410. The result of the comparison enables region control logic 500to select an appropriate supply voltage from a set of available voltagesettings. While FIG. 5 depicts an available selection of two supplyvoltages (VDD0 402 and VDD1 404), another embodiment of the presentinvention may include more than two available input voltages. Stillanother embodiment of the present invention may replace the multiplesupply voltage sources with a single voltage source that includes a“soft switch” that operates as a programmable voltage supply. Eachregion can step up or step down the provided voltage according to theresults of comparator 408.

As depicted, a ring oscillator 502, utilized as a performance monitor,to predict the processing variation in the respective region.Divider/counter 512 measures the frequency of ring oscillator 502. Busdrivers 510 a and 510 b are circuits added to address/control bus 510 aand data bus 510 b to facilitate sufficient drive of a signal to centralcontrol logic 410. Bus drivers 510 a and 510 b are necessary to combatcapacitive loading, which slows down the data propagation rate andprevents proper time sequencing of system operation.

As illustrated, central control logic 410 sends a default signalpropagation frequency via data bus 406. A register 508 stores thedefault signal propagation frequency value sent by central control logic410. When divider/counter 512 predicts the processing variation (e.g.,the signal propagation frequency) of the particular region, a comparator506 compares the actual signal propagation frequency of the region withthe default signal propagation frequency stored in register 508.Alternatively, central control logic 410 can collect all of the measuredring oscillator frequencies (e.g., signal propagation frequency) fromall the regions and then sends a default signal propagation frequencycalculated from the collection of measured ring oscillator frequencies.

FIG. 6 is a high-level logical flowchart depicting a method ofcompensating for on-chip processing variations according to a preferredembodiment of the present invention. As illustrated, the process beginsat step 600 and proceeds to step 602, which depicts each region controllogic 500 measuring the signal propagation frequency of each respectiveregion. As previously discussed, ring oscillator 502 and divider counter512 measure the signal propagation frequency of circuits 504. Theprocess then continues to step 604, which depicts each region controllogic 500 sending the measure of signal propagation frequency of therespective region to central control logic 410. Region control logic 500sends the signal propagation frequency for the respective region viaaddress/control bus 408.

The process then continues to step 606, which illustrates centralcontrol logic 410 assessing the received signal propagation frequenciesfrom each respective region and adjusts the settings of the availablevoltage sources. In one embodiment of the present invention, centralcontrol logic 410 can adjust the voltage settings of the voltagessources VDD0 402 and VDD1 404 in response to the received data from eachrespective region. Those with skill in this art will appreciate thatintegrated circuit 300 may include any number of voltage sources and isnot limited to the two sources (e.g., VDD0 402 and VDD1 404) as depictedin FIG. 5. In another embodiment of the present invention, VDD0 402 andVDD1 404 may be replaced with a single voltage source with the capacityof providing a special voltage setting for each region of integratedcircuit 300 via voltage step-up or step-down circuitry.

The process then continues to step 608, which depicts central controllogic 410 sending to each region a default signal propagation frequency.Central control logic 410 determines the value of the default signalpropagation frequency such that the regions with lower ring oscillatorfrequency measurements can be compensated with a higher voltage supplyand the regions with higher ring oscillator frequencies (e.g., signalpropagation) can be compensated with a lower voltage supply.

The process continues to step 610, which illustrates each region controllogic 500 assigning a signal propagation frequency rating to eachrespective region. As previously discussed, the signal propagationfrequency rating of each region may be measured with a qualitativelabel, such as “fast”, “nominal”, or “slow”. Other ways ofcharacterizing the signal propagation frequency rating of each regioninvolves assigning a value to each region where “0” is nominal and anyinteger (e.g., 1, −1, 2, 4, −6) determines which power setting thespecific region should select in optimizing the design.

The process then proceeds to step 612, which depicts each region controllogic 500 assigning a voltage setting to each respective region thatcorresponds to the assigned signal propagation frequency rating. Aspreviously discussed, comparator 506 in region control logic 500compares the signal from data bus 406 (i.e., the default signalpropagation frequency) to the signal from divider/counter 512 (i.e., themeasured signal propagation frequency) and assigns a voltage settingdepending on the result of the comparison. As depicted in FIG. 5, if themeasured signal propagation frequency is greater than the default signalpropagation frequency, comparator 506 will select the lower voltagesetting. Likewise, if the measured signal propagation frequency is lessthan the default signal propagation frequency, comparator 506 willselect the higher voltage setting. In another embodiment of the presentinvention, there may be more than two available voltage settings.Comparator 506 may be replaced by a selection circuit such as amultiplexer that can choose from multiple (e.g., more than two) voltagesources. The process then returns to step 602 and proceeds in aniterative fashion.

As disclosed, the present invention is a system and method ofcompensating for effects of on-chip processing variation on anintegrated circuit. The integrated circuit is divided into a set ofregions. Then, region control logic, included in each region, predicts aprocessing variation in each respective region of the integratedcircuit. Finally, each region control logic automatically selects one ofa set of available power settings to power each one of the respectiveregions, in response to the region control logic predicting theprocessing variation, wherein the processing variation of each of theset of regions is minimized.

While this invention has been particularly shown as described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention. Itis also important to note that although the present invention has beendescribed in the context of a fully functional computer system, thoseskilled in the art will appreciate that the mechanisms of the presentinvention are capable of being distributed as a program product in avariety of forms, and that the present invention applies equallyregardless of the particular type of signal-bearing media utilized toactually carry out the distribution. Examples of such signal-bearingmedia include, without limitation, recordable-type media such as floppydisks or CD-ROMs and transmission-type media such as analog or digitalcommunication links.

1. A system for compensating for effects of on-chip processing variationon an integrated circuit, wherein said integrated circuit includes aplurality of regions, said system comprising: at least one power supply,coupled to said integrated circuit; a region control logic, fartherincluding: a performance monitor, coupled to said at least one powersupply, said performance monitor for dynamically predicting a signalpropagation frequency of at least one of said plurality of regions; acomparator, coupled to said at least one power supply, for comparingsaid signal propagation frequency with a default signal propagationfrequency and selecting at least one setting of said at least one powersupply to power said plurality of regions to match said signalpropagation frequency with said default signal propagation frequency. asystem clock of known frequency; and a central control logic, forcomparing said known frequency with said signal propagation frequency,and for sending said default signal propagation frequency to at leastone of said plurality of regions.
 2. The system of claim 5, furthercomprising: at least one interconnect coupling said central controllogic and said region control logic; and at least one driver circuit forenhancing a signal propagating on said at least one interconnect.
 3. Thesystem of claim 5, wherein said region control logic farther includes:at least one register for storing said default signal propagationfrequency sent from said central control logic.